Programmable logic devices (PLDs) are programmed with configuration data to provide various user-defined features. For example, a desired functionality may be achieved by programming a configuration memory of a PLD such as a field programmable gate arrays (FPGA) or a complex programmable logic devices (CPLD) with an appropriate configuration data bitstream.
A conventional FPGA includes a data shift register (DSR) to receive the configuration data. Configuration data words are serially shifted into the DSR and then shifted out to configure the appropriate configuration memory cells in the FPGA as determined by an address from a configuration address shift register (ASR). For example, an FPGA typically organizes logic resources such as lookup tables (LUTs) into a plurality of programmable logic blocks. A conventional truth table size for each LUT is sixteen bits. Thus, if each logic block includes four such LUTs, the resulting number of bits necessary to program the configuration memory cells for the truth tables would require 54 bits per programmable logic block. A number of other bits are necessary to complete the programming of a programmable logic block—for example, in one embodiment of an FPGA, each programmable logic block requires 66 configuration memory bits. Thus, a convenient length for the configuration data shift register (DSR) in such an FPGA would match this size so as to be 66 bits long.
But the programmable logic blocks are not the only components in an FPGA that will be configured by configuration data from the configuration DSR. For instance, each input/output (I/O) cell in an FPGA will typically require a certain number of configuration bits to program the I/O cell for the I/O standard being implemented for a given design. Typically, the number of such bits is less than that required for a programmable logic block—for example, in one embodiment, an I/O cell may require 40 bits to complete its configuration. It may thus be seen that a certain number of “phantom” bits will lie in the DSR when a configuration word to configure an I/O cell has been shifted into the DSR. The phantom bits are of course serving no configuration purpose and thus result in undesirable delays.
In addition, the configuration DSR is typically located adjacent the programmable FPGA fabric to be close to the configuration memory cells for this fabric. Routing congestion thus results from the address and data lines that must be directed from the core to the “I/O ring” formed by the plurality of I/O cells. These cells may be considered to form a ring because they associate with the I/O pads that are typically placed circumferentially around the FPGA.
Moreover, the use of the configuration DSR for both the programmable logic block configuration data and the I/O ring configuration data makes the configuration data less repeatable from row-to-row with regard to an external memory providing the configuration data to the PLD being programmed. But it is repeatability that provides the redundancy that can be exploited by configuration data compression schemes. Thus, the external memory must be larger than it would be if the DSR did not have to serve both the core and the I/O ring.
To address these issues in the prior art, FPGAs that provide a separate DSR for the I/O ring have been developed such as disclosed in U.S. Pat. No. 6,842,039. But this separate I/O ring DSR introduces die complexity and cost. Accordingly, there is a need in the art for an improved PLD architecture that addresses the competing configuration needs of the core and the I/O ring.